1. Field of the Invention
The present invention relates to a CAM (Content Addressable Matrix) memory cell and corresponding manufacturing process.
More specifically, the invention relates to a CAM memory cell integrated on a semiconductor substrate of the type comprising a plurality of floating gate memory cells, matrix-organized in rows, called word lines, and columns, called bit lines, said cells belonging to a same row and having floating gate electrodes being short-circuited with each other in order to form a single floating gate electrode for said memory cell of the CAM type.
The invention also relates to a process for manufacturing memory cells of the CAM type integrated on a semiconductor substrate.
The invention particularly relates, but not exclusively, to a CAM (Content Addressable Matrix) memory cell integrated on a semiconductor substrate and having a single floating gate electrode and the following description is made with reference to this field of application for convenience of illustration only.
2. Description of the Related Art
As it is well known, EPROM or FLASH-EPROM electronic memory devices integrated on a semiconductor substrate comprise a plurality of matrix-organized non-volatile memory cells; i.e., the cells are organized in rows, called word lines, and columns, called bit lines.
With reference to FIG. 1, a vertical section along a word line is shown, of a plurality of non-volatile memory cells 1 integrated on a semiconductor substrate 2.
In particular, each single non-volatile memory cell 1 is manufactured in correspondence with a respective active area 1b which is insulated from an adjacent cell along a same word line by means of a thick oxide layer 3. Each single cell 1 comprises a MOS transistor wherein the gate electrode 4, located above a channel region and insulated therefrom by means of a thin oxide layer 5, is floating, i.e., it has a high DC impedance towards all the other terminals of the same cell and of the circuit wherein the cell is inserted.
The cell 1 also comprises a second electrode 6, called control gate, which is coupled to the floating gate electrode 4 and insulated therefrom by means of an interpoly oxide layer 7. The control gate terminal 6, as it is known, is driven by convenient control voltages. The other electrodes of the MOS transistor comprised in the cell 1 are the usual drain, source and body terminals.
It is also known that EPROM or FLASH-EPROM electronic memory devices can comprise memory cells of the CAM (Content Addressable Matrix) type, usually used to register configuration information and to use redundancy in electronic memory devices. In particular, CAM memory cells are manufactured by using a plurality of traditional memory cells and they have a common floating gate terminal hanging over a plurality of channel regions of these traditional cells.
CAM memory cells are generally gathered in a sub-matrix spaced from the memory matrix. In particular, also CAM cells are organized in rows, called word lines, and columns, called bit lines.
A known configuration of a CAM memory cell is shown in FIG. 2, represented in vertical section, along a word line, and globally indicated with 8.
In particular, the CAM memory cell 8 comprises five traditional memory cells whose floating gate electrodes are short-circuited with each other to form a single floating gate electrode 9.
In order to increase the reading current of the CAM memory cell 8, it is known to short-circuit four drain electrodes corresponding t the traditional cells and to use them when reading the CAM memory cell 8, the remaining drain electrode is used for programming. In general, given N traditional cells comprised in the CAM memory cell 8, N-1 are short-circuited with each other and used for reading operations, the remaining drain electrode being available for programming operations. The other body and source electrodes are common to all the cells belonging to the same CAM memory cell, similarly to what happens for the cells of a traditional memory device.
With reference to FIGS. 3 to 6, the process for manufacturing a CAM memory cell 8 is now described, as shown in the sectional view of FIG. 2 taken along the line I-I of FIG. 6.
In particular, FIG. 3 illustrates a thick oxide layer 3a formed on a semiconductor substrate 2a that define active areas 3b of the memory cell 8 (FIG. 2), according to the prior art.
Next, referring back to FIG. 2, a thin gate oxide layer 5a is grown, and a first polysilicon layer, called POLY 1, is then deposited and doped.
Through a traditional photolithographic technique the first polysilicon layer POLY 1 is etched to define a first size C, along word lines, of the single floating gate electrode 9 of the CAM memory cell 8. In particular, a first photolithographic mask 9a is used, shown in FIG. 4.
A second size D of the single floating gate electrode 9 is then defined by using a second photolithographic mask 9b, as shown in FIG. 5.
FIG. 6 shows instead an overlapping of the masks 9a and 9b being used wherein the outlines of a plurality of single floating gate electrodes 9 of CAM memory cells 8 are highlighted with thick strokes.
The prior art manufacturing process goes on by foreseeing, traditionally after defining the single floating gate electrodes 9, the growth of an interpoly oxide layer 7a, typically comprising a series of oxide/nitride/oxide layers, called ONO, and the deposition and further etching of a second polysilicon layer to define a control gate electrode 6a of the CAM memory cell 8, as shown in FIG. 2.
The implants for manufacturing the source and drain electrodes of CAM cells 8 formed on the substrate 2a are then manufactured. The memory device is then completed by means of convenient metallization layers.
Although advantageous under several aspects, this known solution has several drawbacks.
In fact, as it can be noticed by comparing FIGS. 1 and 2, the ONO layer 7a area between polysilicon layers, POLY 1 and POLY 2, of the CAM memory cell 8, being said area represented in FIG. 2 along a size and being the other size given by the length D of the single floating gate electrode 9 is smaller than the corresponding area of the sum of the ONO layers 7 of five traditional matrix cells due to the contributions of the thickness A and of the distance B between the electrodes 4 of traditional memory cells 1.
Therefore, it results that the capacitance CPP,CAM of the CAM memory cell 8 between the first and second polysilicon layers, which is proportional to the area of the ONO layer 7a covering the floating gate electrode 9, is lower than the capacitance CPP,5MatrixCells between the first and second polysilicon layer of five traditional memory cells 1. The other capacitances seen by the floating gate electrodes, 4 and 9 respectively, are instead identical in both cases.
The capacitive coupling αG is defined as the ratio between the capacitance CPP between the first and second polysilicon layers and the overall capacitance CTOT of the cell (i.e., αG=CPP/CTOT). Given that the capacitive coupling αG of the five traditional memory cells is equal to the coupling of a single memory cell, i.e.:CPP,5MatrixCells/CTOT,5MatrixCells=CPP,1MatrixCell/CTOT,1MatrixCell,and the difference in areas between the ONO layer 7a of the CAM memory cell 8 and the ONO layer 7 of a traditional cell 1, a capacitive coupling between the control electrode 6a and the single floating gate electrode 9 of the CAM memory cell 8 is lower than a capacitive coupling between the control gate terminal 6 and the gate electrode 4 of the single traditional matrix cell 1, i.e.:αG,CAM=CPP,CAM/CTOT,CAM<αG,1MatrixCell=CPP,1 MatrixCell/CTOT, 1 MatrixCell.
The known configuration of the CAM memory cells 8 thus implies less efficient performances, mainly a considerable extension of cancellation times with respect to a traditional cell 1.